Example embodiments relate generally to semiconductor integrated circuits, and more particularly to bidirectional delay circuits and to integrated circuits including bidirectional delay circuits.
The demand for efficient design of semiconductor integrated circuits increases with performance enhancements and higher degrees of integration. Typically, in a semiconductor integrated circuit, a complementary metal oxide semiconductor (CMOS) inverter chain is used to achieve a relatively short signal delay time, and a resister-capacitor (RC) delay circuit is used to achieve a relatively long signal delay time. However, the delay time of the RC delay circuit is influenced by variations in manufacturing processes and temperature, which makes it is difficult to implement an exact delay time. Also, the RC delay circuit exhibits low efficiency in terms of chip size.
In addition, the on-current of a transistor increases as the manufacturing process is scaled down, and the increased on-current has an negative effect on a delay circuit for realizing a long delay time. As the integration degree of the semiconductor integrated circuit increases, loads of signal lines increase, and thus the longer delay time may be required. For example, in case of a semiconductor memory device, loads of word lines and bit lines increase according to an increase of its memory capacity, and the larger pulse width or the longer delay time may be required read and write operational margin. The size of the delay circuit increases as the required delay time increases, which results in an increase of an entire size of the integrated circuit and limits a design margin.